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Ordering number : ENA0892
LC87F5M64A
Overview
CMOS IC FROM 64K byte, RAM 2048 byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC87F5M64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable), 2048-byte RAM, On-chip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 27-source 10-vector interrupt feature.
Features
Flash ROM * Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source * Block-erasable in 128 byte units * 65536 x 8 bits RAM * 2048 x 9 bits Minimum Bus Cycle Time * 83.3ns (12MHz) VDD=2.8 to 5.5V * 125ns (8MHz) VDD=2.5 to 5.5V * 500ns (2MHz) VDD=2.2 to 5.5V Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) * 250ns (12MHz) VDD=2.8 to 5.5V * 375ns (8MHz) VDD=2.5 to 5.5V * 1.5s (2MHz) VDD=2.2 to 5.5V Ports * Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units * Normal withstand voltage input port * Dedicated oscillator ports * Reset pins * Power pins
46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn, PWM2, PWM3, XT2) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Ver.1.00
80807HKIM 20070702-S00003 No. A0892-1/22
LC87F5M64A
Timers * Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) x2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) * Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz). 2) Can generate output real-time. SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART: 2 channels * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2 bit in continuous data transmission) * Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) AD Converter: 8 bits x 11 channels PWM: Multifrequency 12-bit PWM x 2 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) 1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. Watchdog Timer * External RC watchdog timer * Interrupt and reset signals selectable
No.A0892-2/22
LC87F5M64A
Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts * 27 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer0/base timer1 T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/UART2 receive SIO/UART1 transmit/UART2 transmit ADC/T6/T7 Port 0/T4/T5/PWM2, PWM3 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions * 16-bits x 8-bits (5 tCYC execution time) * 24-bits x 16-bits (12 tCYC execution time) * 16-bits / 8-bits (8 tCYC execution time) * 24-bits / 16-bits (12 tCYC execution time) Oscillation Circuits * RC oscillation circuit (internal) * CF oscillation circuit * Crystal oscillation circuit * Multifrequency RC oscillation circuit (internal)
: For system clock : For system clock, with internal Rf : For low-speed system clock : For system clock
System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 250ns, 500ns, 1.0s, 2.0s, 4.0s, 8.0s, 16.0s, 32.0s, and 64.0s (at a main clock rate of 12MHz).
No.A0892-3/22
LC87F5M64A
Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt. * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit On-chip Debugger Function * Permits software debugging with the test device installed on the target board. Package Form * QIP64E (14 x 14)
: "Lead-free type"
Development Tools * Evaluation (EVA) chip * Emulator * On-chip-debugger Programming Boards
Package QIP64E(14 x 14)
: LC87EV690 : EVA62S + ECB876600D + SUB875M00 + POD64QFP ICE-B877300 + SUB875M00 + POD64QFP : TCB87-TypeB + LC87F5M64A
Programming boards W87F50256Q
Flash ROM Programmer
Maker Flash Support Group, Inc.(Single) Flash Support Group, Inc.(Gang) Model AF9708/09/09B (including product of Ando Electric Co.,Ltd) AF9723(Main body) (including product of Ando Electric Co.,Ltd) AF9833(Unit) (including product of Ando Electric Co.,Ltd) SKK/SKK Type-B/SKK DBG Type-B (SANYO FWS) Support version(Note) Revision : After Rev.02.73 Device LC87F6D64A
Application Version:
-
SANYO
After 1.04 Chip Data Version: After2.10
LC87F5M64A
No.A0892-4/22
LC87F5M64A
Package Dimensions
unit : mm (typ) 3159A
17.2 14.0 48 49 33 32
14.0
64 1 0.8 (1.0)
(2.7)
17 16 0.35 0.15
3.0max
0.1
SANYO : QIP64E(14X14)
17.2
0.8
PC5/DBGP0
PC6/DBGP1
Pin Assignment
P83/AN3 P84/AN4 P85/AN5 P86/AN6 PC0 PC1 PC2 PC3 PC4
PC7/DBGP2
VDD3
VSS3
P30
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P12/SCK0 2 P13/SO1 3 P14/SI1/SB1 4 P15/SCK1 5 P16/T1PWML 6 P17/T1PWMH/BUZ 7 PWM2 8 PWM3 9 10 11 12 13 14 15 16 P05/CKO VDD2 VSS2 P00 P01 P02 P03 P04 Top view 32 31 30 29 28 27 26 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 P36 P37 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN/INT7 P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN/INT6 P07/T7O P06/T6O
P31 25 24 23 22 21 20 19 18 17
LC87F5M64A
SANYO: QIP64E(14x14) "Lead-free Type"
No.A0892-5/22
LC87F5M64A
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF RC X'tal MRC Clock generator
Flash ROM
PC SIO0 Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7 ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to INT7 Noise filter Port 3
RAR
Base timer
RAM
PWM2/3
Port C
Stack pointer
UART1
Watchdog timer
UART2
On-chip Debugger
No.A0892-6/22
LC87F5M64A
Pin Description
Pin Name VSS1, VSS2 VSS3 VDD1, VDD2 VDD3 Port 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin * 8-bit I/O port * I/O specifiable in 4-bit units * Pull-up resistor can be turned on and off in 4-bit units * HOLD release input * Port 0 interrupt input * Shared Pins P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Port 2 P20 to P27 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Other functions P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT7 input/timer 0H capture 1 input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input * Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Description Option No No Yes
Continued on next page.
No.A0892-7/22
LC87F5M64A
Continued from preceding page.
Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Shared Pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input port: AN8 (P70), AN9 (P71) * Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No
Port 8 P80 to P86
I/O
* 7-bit I/O port * I/O specifiable in 1-bit units * Shared Pins AD converter input port : AN0 (P80) to AN6 (P86)
No
PWM2 PWM3 Port 3 P30 to P37
I/O I/O
* PWM2 and PWM3 output ports * General-purpose I/O available * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive
No Yes
Port C PC0 to PC7
I/O
* 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistor can be turned on and off in 1-bit units * Pin functions DBGP0 to DBGP2(PC5 to PC7): On-chip Debugger
Yes
RES XT1
Input Input
Reset pin * 32.768kHz crystal oscillator input pin * Shared pins General-purpose input port AD converter input port : AN10 Must be connected to VDD1 if not to be used. * 32.768kHz crystal oscillator input pin * Shared pins General-purpose I/O port AD converter input port : AN11 Must be set for oscillation and kept open if not to be used.
No No
XT2
I/O
No
CF1 CF2
Input Output
Ceramic resonator input pin Ceramic resonator output pin
No No
No.A0892-8/22
LC87F5M64A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port P00 to P07 Options Selected in Units of 1 bit Option Type 1 2 P10 to P17 1 bit 1 2 P20 to P27 1 bit 1 2 P70 P71 to P73 P80 to P86 PWM2, PWM3 P30 to P37 1 bit No No No No 1 2 PC0 to PC7 1 bit 1 2 XT1 XT2 No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS CMOS Nch-open drain CMOS Nch-open drain Input for 32.768kHz crystal oscillator (Input only) Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable Programmable No No Programmable Programmable Programmable Programmable No No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). *1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. (Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup capacitors.
Back-up capacitor Power Supply LSI VDD1
VDD2
VDD3 VSS1 VSS2 VSS3
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up capacitor Power Supply LSI VDD1
VDD2
VDD3 VSS1 VSS2 VSS3
No.A0892-9/22
LC87F5M64A
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Maximum supply voltage Input voltage Input/Output voltage VI(1) VIO(1) XT1, CF1 Ports 0, 1, 2 Ports 7, 8 Ports 3, C PWM0, PWM1, XT2 Peak output current IOPH(2) IOPH(3) Mean output High level output current current (Note1-1) IOMH(2) IOMH(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) Peak output current IOPL(1) IOMH(1) IOPH(1) Ports 0, 1, 2 Ports 3, C PWM2, PWM3 P71 to P73 Ports 0, 1, 2 Ports 3, C PWM2, PWM3 P71 to P73 P71 to P73 Ports, 1 PWM2, PWM3 Ports 0, 2 Ports 0, 1, 2 PWM2, PWM3 Port 3 Ports C Ports 3, C P02 to P07 Ports 1, 2 Ports 3, C PWM2, PWM3 IOPL(2) IOPL(3) Mean output current (Note1-1) Low level output current IOML(2) IOML(3) Total output current IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) IOAL(8) IOAL(9) Maximum power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 Pd max IOAL(1) IOML(1) P00, P01 Ports 7, 8, XT2 P02 to P07 Ports 1, 2 Ports 3, C PWM2, PWM3 P00, P01 Ports 7, 8, XT2 Port 7 P83 to P86, XT2 P80 to P82 Ports 7, 8, XT2 Ports 1 PWM2, PWM3 Ports 0, 2 Ports 0, 1, 2 PWM2, PWM3 Port 3 Ports C Ports 3, C QIP64E(14x14) Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta=-40 to +85C Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 application pin. Per 1 application pin. Total of all applicable pins 20 7.5 15 15 20 45 45 80 45 45 80 300 +85 C +125 mW Per 1 application pin. Per 1 application pin. Per 1 application pin. 15 30 10 Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 application pin. 20 mA Total of all applicable pins Total of all applicable pins CMOS output select Per 1 application pin Per 1 application pin. Per 1 application pin. CMOS output select Per 1 application pin Per 1 application pin Per 1 application pin Total of all applicable pins Total of all applicable pins -10 -20 -5 -7.5 -10 -3 -10 -25 -25 -45 -25 -25 -45 -0.3 VDD+0.3 Symbol VDD max Pins/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0892-10/22
LC87F5M64A
Recommended Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage (Note2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2 P71 to P73 P70 port input/ interrupt side VIH(2) VIH(3) VIH(4) Low level input voltage VIL(1) Ports 0, 8, 3, C PWM2, PWM3 P70 watchdog timer side XT1, XT2, CF1,RES Ports 1, 2 P71 to P73 P70 port input/ Interrupt side VIL(2) Ports 0, 8, 3, C PWM2, PWM3 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 5.5 VIL(3) VIL(4) Instruction cycle time (Note2-2) External system clock frequency FEXCF(1) CF1 * CF2 pin open * System clock frequency division rate=1/1 * External system clock duty=505% * CF2 pin open * System clock frequency division rate=1/2 Oscillation frequency range (Note2-3) FmCF(3) FmRC FmMRC FsX'tal XT1, XT2 CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 8MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation See Fig. 1. Internal RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal oscillation See Fig. 2. 2.8 to 5.5 2.5 to 5.5 2.2 to 5.5 2.8 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 2.5 to 5.5 2.2 to 5.5 0.3 0.2 0.1 0.1 12 8 4 1.0 16 32.768 kHz 2.0 MHz 24.4 16 4 2.2 to 5.5 0.1 2 MHz tCYC Port 70 watchdog timer side XT1, XT2, CF1, RES 2.2 to 4.0 2.2 to 5.5 2.8 to 5.5 2.5 to 5.5 2.2 to 5.5 2.8 to 5.5 2.5 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS 0.245 0.367 1.47 0.1 0.1 VDD VDD VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 200 12 8 s V 2.2 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 Symbol VDD(1) Pins/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.245s tCYC200s 0.367s tCYC200s 1.47s tCYC200s RAM and register contents sustained in HOLD mode 2.0 5.5 min 2.8 2.5 2.2 Specification typ max 5.5 5.5 5.5 unit
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0892-11/22
LC87F5M64A
Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pins/Remarks Ports 0, 1, 2 Ports 7, 8 Ports 3, C RES PWM2, PWM3 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 CF1 Ports 0, 1, 2 Ports 7, 8 Ports 3, C RES PWM2, PWM3 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2, 7 Ports 3, C RES Ports 1, 2, 7 All pins * For pins other than that under test: VIN=VSS * f=1MHz * Ta=25C 2.2 to 5.5 10 pF Ports 0, 1, 2 Ports 3, C PWM2, PWM3, Ports 7, 8 XT2 P00, P01 PWM2, PWM3 Ports 71 to 73 XT1, XT2 CF1 Ports 0, 1, 2 Ports 3, C Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current)) For input port specification VIN=VDD VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current)) For input port specification VIN=VSS VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA IOL=30mA IOL=5mA IOL=2.5mA VOH=0.9VDD 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 2.2 to 5.5 2.2to 5.5 15 18 35 35 0.1VDD -1 -15 VDD-1 VDD -0.4 VDD -0.4 VDD -0.4 VDD -0.4 VDD -1.5 VDD -0.4 VDD -0.4 1.5 0.4 0.4 0.4 0.4 1.5 0.4 0.4 80 150 V k V 2.2 to 5.5 -1 2.2 to 5.5 2.2 to 5.5 1 15 A 2.2 to 5.5 1 min Specification typ max unit
No.A0892-12/22
LC87F5M64A
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/reception mode Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) 2.2 to 5.5 Output Input clock delay time tdD0(2) tdD0(1) SO0(P10), SB0(P11), * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) tdD0(3) Output clock * (Note 4-1-3) (1/3)tCYC +0.15 2.2 to 5.5 2.2 to 5.5 0.03 * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.2 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pins /Remarks SCK0(P12) * See Fig. 6. Conditions VDD[V] min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 s 1tCYC +0.05
Serial output
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
No.A0892-13/22
LC87F5M64A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14) SB1(P14), Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK * See fig. 6. 2.2 to 5.5 0.03 Output delay Serial output time tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected. * See Fig. 6. 2.2 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pins/ Remarks SCK1(P15) * See Fig. 6. Conditions VDD[V] min 2 2.2 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Serial clock
No.A0892-14/22
LC87F5M64A
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P20 to P23), INT5(P24 to P27), INT6(P20) INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1. INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. Resetting is enabled. 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2 64 256 200 s tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 min Specification typ max unit
AD Converter Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pins/Remarks AN0(P80) to AN6(P86), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2), AD conversion time=32xtCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 11.74 (tCYC= 0.367s) 23.53 3.0 to 5.5 AD conversion time=64xtCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 (tCYC= 0.735s) 15.68 (tCYC= 0.245s) 23.49 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.367s) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) VDD 1 V A s max unit bit LSB
Note 6-1: The quantization error (1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0892-15/22
LC87F5M64A
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pins/Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=12MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(2) * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 8MHz side IDDOP(3) * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(4) * FmCF=4MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode IDDOP(5) * System clock set to 4MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDOP(6) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode IDDOP(7) * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDOP(8) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. * System clock set to 1MHz with frequency IDDOP(9) variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDOP(10) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDOP(11) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. HALT mode consumption current (Note 7-1) IDDHALT(1) VDD1 =VDD2 =VDD3 * HALT mode * FmCF=12MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDHALT(2) * HALT mode * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode IDDHALT(3) * System clock set to 8MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. 2.5 to 4.5 12.5 2.8 4.5 to 5.5 2.4 5.3 2.8 to 5.5 1.8 4 mA 4.5 to 5.5 3.2 7.5 2.2 to 4.5 19 70 A 4.5 to 5.5 38 110 2.2 to 4.5 0.67 4.2 4.5 to 5.5 1.25 5.2 2.2 to 4.5 0.53 3.0 4.5 to 5.5 0.95 4.3 2.2 to 4.5 1.45 3.8 4.5 to 5.5 2.7 6 mA 2.5 to 4.5 3.8 10 4.5 to 5.5 6.7 14 2.8 to 4.5 5.3 13.5 4.5 to 5.5 9.1 18.5 min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors
Continued on next page.
No.A0892-16/22
LC87F5M64A
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) IDDHALT(5) Symbol IDDHALT(4) Pins/Remarks VDD1 =VDD2 =VDD3 * HALT mode * FmCF=4MHz ceramic oscillation mode * FmX'tal=32.768kHz by crystal oscillation mode * System clock set to 4MHz side * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/1 frequency division ratio. IDDHALT(6) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode IDDHALT(7) * System clock set to internal RC oscillation * frequency variable RC oscillation stopped *1/2 frequency division ratio. IDDHALT(8) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDHALT(9) * System clock set to 1MHz with frequency variable RC oscillation * Internal RC oscillation stopped * 1/2 frequency division ratio. IDDHALT(10) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz by crystal oscillation mode. IDDHALT(11) * System clock set to 32.768kHz side. * Internal RC oscillation stopped * frequency variable RC oscillation stopped * 1/2 frequency division ratio. HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 * HOLD mode * CF1=VDD or open (External clock mode) 2.2 to 4.5 * Timer HOLD mode * CF1=VDD or open (External clock mode) * FmX'tal=32.768kHz by crystal oscillation mode 4.5 to 5.5 2.2 to 4.5 0.01 16 3.5 14 63 50 4.5 to 5.5 0.03 18 2.2 to 4.5 5 63 A 4.5 to 5.5 18 70 2.2 to 4.5 0.5 2.7 4.5 to 5.5 1 3.8 2.2 to 4.5 0.17 0.7 mA 4.5 to 5.5 0.33 0.9 2.2 to 4.5 0.5 1.3 4.5 to 5.5 1 2.3 Conditions VDD[V] min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors
F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = 0V
Parameter Onboard programming current Programming time tFW(1) tFW(2) * Erasing * programming 2.7 to 5.5 2.7 to 5.5 20 40 30 60 ms s Symbol IDDFW(1) Pins/Remarks VDD1 Conditions VDD[V] * Without CPU current 2.70 to 5.5 5 10 mA min Specification typ max unit
No.A0892-17/22
LC87F5M64A
UART (Full Duplex) Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Transfer rate Symbol UBR Pins/Remarks P32 (UTX1), P33 (URX1), P34 (UTX2), P35 (URX2) 2.5 to 5.5 16/3 8192/3 tCYC Conditions VDD[V] min Specification typ max unit
Data length : 7/8/9 bits (LSB first) Stop bits : 1-bit (2-bit in continuous data transmission) Parity bits : None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Start bit Start of reception Receive data (LSB first) Stop bit End of reception
UBR
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below. * Place capacitors as close to VDD1 and VSS1 as possible. * Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1', L2 = L2'). * Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. * Capacitance of C2 must be more than 0.1F. * Use thicker pattern for VDD1 and VSS1.
L2 L1 VSS1 C1 C2
VDD1 L1'
L2'
No.A0892-18/22
LC87F5M64A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal Frequency 12MHz 10MHz MURATA 8MHz Vendor Name Circuit Constant Oscillator Name C1 [pF] CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 4MHz CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (10) (15) (15) (15) C2 [pF] (10) (10) (15) (10) (15) (15) (15) Rf1 [] Open Open Open Open Open Open Open Rd1 [] 470 470 680 680 1k 1.5k 1.5k Operating Voltage Range [V] 2.6 to 5.5 2.4 to 5.5 2.6 to 5.5 2.3 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 0.05 0.05 0.05 max [ms] Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency Vendor Name SEIKO TOYOCOM Circuit Constant Oscillator Name C3 [pF] 32.768kHz MC-306 18 C4 [pF] 18 Rf2 [] Open Rd2 [] 560k Operating Voltage Range [V] 2.2 to 5.5 Oscillation Stabilization Time typ [s] 1.2 max [s] 3.0 Applicable CL value=12.5pF Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure. 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1 Rf
CF2
XT1 Rd1
XT2
Rf Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0892-19/22
LC87F5M64A
VDD Power supply Operating VDD lower limit 0V Reset time RES
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal VALID
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times
No.A0892-20/22
LC87F5M64A
VDD
RRES
RES CRES
Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the IC's operating voltage.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (SIO0 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKLA SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0892-21/22
LC87F5M64A
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This catalog provides information as of June, 2007. Specifications and information herein are subject to change without notice.
PS No.A0892-22/22

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